343 lines
7.8 KiB
C
343 lines
7.8 KiB
C
/*
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* Copyright (C) 2019 Kai Ludwig, DG4KLU
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* Copyright (C) 2019-2025 Roger Clark, VK3KYY / G4KYF
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*
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. Use of this source code or binary releases for commercial purposes is strictly forbidden. This includes, without limitation,
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* incorporation in a commercial product or incorporation into a product or project which allows commercial use.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <stdbool.h>
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#include "interfaces/hr-c6000_spi.h"
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#include "main.h"
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volatile bool SPI0inUse = false;
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volatile bool SPI1inUse = false;
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void SPIInit(void)
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{
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}
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void SPI0Setup(void)
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{
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//SPIO is a bit-banged interface on the MD9600
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}
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void SPI1Setup(void)
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{
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//SPI1 is a hardware Interface on the MD9600
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}
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int SPI0WritePageRegByte(uint8_t page, uint8_t reg, uint8_t val)
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{
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uint8_t txBuf[3];
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UBaseType_t SavedInterruptStatus;
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if (SPI0inUse)
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{
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return -1;
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}
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SavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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SPI0inUse = true;
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txBuf[0] = page;
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txBuf[1] = reg;
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txBuf[2] = val;
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SPI0Write(txBuf,3);
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SPI0inUse = false;
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taskEXIT_CRITICAL_FROM_ISR(SavedInterruptStatus);
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return 0;
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}
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int SPI0WritePageRegByteExtended(uint8_t page, uint16_t reg, uint8_t val)
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{
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uint8_t txBuf[4];
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UBaseType_t SavedInterruptStatus;
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if (SPI0inUse)
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{
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return -1;
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}
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SavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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SPI0inUse = true;
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txBuf[0] = page | 0x40;
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txBuf[2] = (reg >> 8) & 0x07;
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txBuf[1] = reg & 0xFF;
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txBuf[3] = val;
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SPI0Write(txBuf,4);
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SPI0inUse = false;
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taskEXIT_CRITICAL_FROM_ISR(SavedInterruptStatus);
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return 0;
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}
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int SPI0ReadPageRegByte(uint8_t page, uint8_t reg, volatile uint8_t *val)
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{
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uint8_t rxBuf[3];
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uint8_t txBuf[3];
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UBaseType_t SavedInterruptStatus;
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if (SPI0inUse)
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{
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return -1;
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}
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SavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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SPI0inUse = true;
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txBuf[0] = page | 0x80;
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txBuf[1] = reg;
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txBuf[2] = 0xFF;
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SPI0Read(txBuf, rxBuf, 3);
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*val = rxBuf[2];
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SPI0inUse = false;
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taskEXIT_CRITICAL_FROM_ISR(SavedInterruptStatus);
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return 0;
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}
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int SPI0ClearPageRegByteWithMask(uint8_t page, uint8_t reg, uint8_t mask, uint8_t val)
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{
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int status;
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uint8_t tmp_val;
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status = SPI0ReadPageRegByte(page, reg, &tmp_val);
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if (status == kStatus_Success)
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{
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tmp_val = val | (tmp_val & mask);
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status = SPI0WritePageRegByte(page, reg, tmp_val);
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}
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return status;
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}
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int SPI0WritePageRegByteArray(uint8_t page, uint8_t reg, const uint8_t *values, uint8_t length)
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{
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const int SPI0_PAGE_WRITE_BUFFER_SIZE = 128 + 2;
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uint8_t txBuf[SPI0_PAGE_WRITE_BUFFER_SIZE + 2];
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UBaseType_t SavedInterruptStatus;
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if (length > SPI0_PAGE_WRITE_BUFFER_SIZE)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI0inUse)
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{
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return -1;
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}
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SavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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SPI0inUse = true;
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txBuf[0] = page;
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txBuf[1] = reg;
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memcpy(txBuf + 2, values, length);
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SPI0Write(txBuf, length + 2);
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SPI0inUse = false;
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taskEXIT_CRITICAL_FROM_ISR(SavedInterruptStatus);
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return 0;
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}
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int SPI0ReadPageRegByteArray(uint8_t page, uint8_t reg, volatile uint8_t *values, uint8_t length)
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{
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uint8_t rxBuf[0x60 + 2];
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uint8_t txBuf[0x60 + 2];
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UBaseType_t SavedInterruptStatus;
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if (length > 0x60)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI0inUse)
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{
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return -1;
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}
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SavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR();
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SPI0inUse = true;
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txBuf[0] = page | 0x80;
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txBuf[1] = reg;
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SPI0Read(txBuf, rxBuf, length + 2);
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for (int i = 0; i < length; i++)
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{
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values[i] = rxBuf[i + 2];
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}
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SPI0inUse = false;
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taskEXIT_CRITICAL_FROM_ISR(SavedInterruptStatus);
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return 0;
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}
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void SPI0Write(uint8_t *txBuf, uint8_t length)
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{
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uint8_t val;
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//Set the CS pin Low
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HAL_GPIO_WritePin(DMR_SPI_CS_GPIO_Port,DMR_SPI_CS_Pin, GPIO_PIN_RESET);
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for(int v = 0; v < length; v++)
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{
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val = txBuf[v];
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for (register int i = 0; i < 8; i++)
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{
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HAL_GPIO_WritePin(DMR_SPI_MOSI_GPIO_Port, DMR_SPI_MOSI_Pin, ((val & 0x80) != 0));
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#ifdef SPI_0_DELAYS
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for(volatile int x=0;x<1;x++);
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#endif
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HAL_GPIO_WritePin(DMR_SPI_CLK_GPIO_Port, DMR_SPI_CLK_Pin, GPIO_PIN_RESET);
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#ifdef SPI_0_DELAYS
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for(volatile int x=0;x<1;x++);
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#endif
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val = val << 1;
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HAL_GPIO_WritePin(DMR_SPI_CLK_GPIO_Port, DMR_SPI_CLK_Pin, GPIO_PIN_SET);
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#ifdef SPI_0_DELAYS
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for(volatile int x=0;x<1;x++);
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#endif
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}
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}
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//Set the CS pin high again
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HAL_GPIO_WritePin(DMR_SPI_CS_GPIO_Port, DMR_SPI_CS_Pin, GPIO_PIN_SET);
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}
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void SPI0Read(uint8_t *txBuf, uint8_t *rxBuf, uint8_t length)
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{
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uint8_t val;
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uint8_t rxval;
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//Set the CS pin Low
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HAL_GPIO_WritePin(DMR_SPI_CS_GPIO_Port,DMR_SPI_CS_Pin, GPIO_PIN_RESET);
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for(int v = 0; v < length; v++)
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{
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val = txBuf[v];
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rxval = 0;
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for (register int i = 0; i < 8; i++)
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{
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HAL_GPIO_WritePin(DMR_SPI_MOSI_GPIO_Port, DMR_SPI_MOSI_Pin, ((val & 0x80) != 0));
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HAL_GPIO_WritePin(DMR_SPI_CLK_GPIO_Port, DMR_SPI_CLK_Pin, GPIO_PIN_RESET);
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val = val << 1;
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rxval = (rxval << 1) + (HAL_GPIO_ReadPin(DMR_SPI_MISO_GPIO_Port, DMR_SPI_MISO_Pin) != 0);
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HAL_GPIO_WritePin(DMR_SPI_CLK_GPIO_Port, DMR_SPI_CLK_Pin, GPIO_PIN_SET);
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}
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rxBuf[v] = rxval;
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}
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//Set the CS pin high again
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HAL_GPIO_WritePin(DMR_SPI_CS_GPIO_Port,DMR_SPI_CS_Pin, GPIO_PIN_SET);
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}
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int SPI1WritePageRegByteArray(uint8_t page, uint8_t reg, const uint8_t *values, uint8_t length)
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{
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uint8_t txBuf[32 + 2];
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if (length > 32)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI1inUse)
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{
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return -1;
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}
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SPI1inUse = true;
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// dspi_transfer_t masterXfer;
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int status = kStatus_Fail;
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txBuf[0] = page;
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txBuf[1] = reg;
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memcpy(txBuf + 2, values, length);
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HAL_GPIO_WritePin(V_SPI_CS_GPIO_Port, V_SPI_CS_Pin, GPIO_PIN_RESET);
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status = HAL_SPI_Transmit(&hspi2, txBuf, length + 2, HAL_MAX_DELAY);
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HAL_GPIO_WritePin(V_SPI_CS_GPIO_Port, V_SPI_CS_Pin, GPIO_PIN_SET);
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SPI1inUse = false;
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return status;
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}
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int SPI1ReadPageRegByteArray(uint8_t page, uint8_t reg, volatile uint8_t *values, uint8_t length)
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{
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uint8_t rxBuf[32 + 2];
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uint8_t txBuf[32 + 2];
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if (length > 32)
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{
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return kStatus_InvalidArgument;
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}
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if (SPI1inUse)
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{
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return -1;
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}
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SPI1inUse = true;
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// dspi_transfer_t masterXfer;
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HAL_StatusTypeDef status;
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txBuf[0] = page | 0x80;
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txBuf[1] = reg;
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HAL_GPIO_WritePin(V_SPI_CS_GPIO_Port, V_SPI_CS_Pin, GPIO_PIN_RESET);
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status = HAL_SPI_TransmitReceive(&hspi2, txBuf, rxBuf, length + 2, HAL_MAX_DELAY);
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HAL_GPIO_WritePin(V_SPI_CS_GPIO_Port, V_SPI_CS_Pin, GPIO_PIN_SET);
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if (status == HAL_OK)
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{
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for (int i = 0; i < length; i++)
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{
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values[i] = rxBuf[i + 2];
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}
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}
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SPI1inUse = false;
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return status;
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}
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